1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory, and more particularly to an SWL(Split Word Line) ferroelectric memory without plate lines and a circuit for driving the same.
2. Discussion of the Related Art
Ferroelectric random access memory(FRAM) having a data processing speed as fast as DRAM which is generally used as a semiconductor memory and for conserving data even at turn off of power is paid attention as a memory of the next generation. Alike the DRAM, the FRAM uses capacitors as memory cells, but with capacitors of a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not cleared off even after clearing off of an electric field applied thereto.
FIG. 1a illustrates a general hysteresis loop of a ferroelectric substance, and FIG. 1b illustrates a structure of a unit capacitor in a background art ferroelectric memory.
Referring to FIG. 1a, it can be known that a polarization induced by an electric field is, not vanished, but remained of a certian portion("d" or "a" state) even after clear off of the electric field due to existence of a spontaneous polarization. These "d" and "a" states may be matched to "1" and "0", for being utilized as a memory cell. In other words, referring to FIG. 1b, the state in which a positive voltage is applied to a node 1 is a state of "c" in FIG. 1a, the state in which no voltage is applied to the node 1 is a state of "d". Opposite to this, if a negative voltage is applied to the node 1, the state moves from "d" to "f". If no voltage is applied to the node 1, the state moves to "a", and, if a positive voltage is applied again, the states moves to "c" via "b". At the end, even if there is no voltage applied on both ends of a capacitor, a data can be stored in stable states of "a" and "b". On the hysteresis loop, "c"-"d" state is a state of logic value "1", and "a"-"f" state is a state of logic value "0".
In reading a data from the capacitor, the "d" state is canceled to read the data stored in the capacitor. In a background art, a sense amplifier is used for reading a data using a voltage generated in a reference voltage generator and a voltage generated in a main cell arry. In a ferroeletric reference cell, two modes of "1" polarity and "0" polarity are used for generating a reference voltage on a reference bit line. Accordingly, the sense amplifier compares a bit line voltage on a main cell and a reference bit line voltage on a reference cell, to read information in the main cell. By rewriting the read data within the same cycle, the canceled data can be recovered.
A background art FRAM will be explained with reference to the attached drawings. There are IT/IC FRAM having a transistor and a capacitor in a unit cell and 2T/2C FRAM having two transistors and two capacitors. FIG. 2 illustrates a background art 1T/IC FRAM cell array.
Referring to FIG. 2, the background art 1T/IC FRAM cell array is provided with a plurality of wordlines W/L arranged in one direction spaced at fixed intervals, a plurality of platelines P/L arranged between wordlines in parallel thereto, and a plurality of bitlines B1, - - - , Bn arranged in a direction vertical to each of the wordlines W/L and the platelines P/L spaced at fixed intervals. Each of the transistors in a unit memory cell has a gate electrode connected to one of the wordlines W/L, a source electrode connected an adjacent bitline B/L, and a drain electrode connected to a first electrode of the capacitor and a second electrode of the capacitor connected to an adjacent plateline P/L.
A driving circuit and operation of the aforementioned background art 1T/1C FRAM will be explained. FIGS. 3a and 3b together illustrate a circuit for driving the background art 1T/1C FRAM, FIG. 4a illustrates timings of signals provided for explaining a writing on the background art 1T/1C FRAM cell, and FIG. 4b illustrates timings of signals provided for explaining a reading from the background art 1T/1C FRAM cell.
The circuit for driving the background art 1T/1C FRAM is provided with a reference voltage generating part 1 for generating a reference voltage, a reference voltage stabilizing part 2 having a plurality of transistors Q1.about.Q4 and a capacitor C1 for stabilzing a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generating part 1 can not be provided to a sense amplifier directly, a first reference voltage storage part 3 having a plurality of transistors Q6.about.Q7 and capacitors C2.about.C3 for being in storage of a logic value "1" and a logic value "0" in adjacent bit lines, a first equalizing part 4 having a transistor Q5 for equalizing adjacent two bitlines, a first main cell array part 5 having a plurality of transistors Q8, Q9, - - - , and ferroelectric capacitors C5, C6, - - - , connected to wordlines W/L and platelines P/L for storing data, a first sense amplifier part 6 having a plurality of transistors Q10.about.Q15 and P-sense amplifiers PSA for sensing a data in a cell selected by the wordline from the plurality of cells in the main cell array part 5, a second main cell array part 7 having a plurality of transistors Q26, Q27, - - - , and capacitors C7, C8, - - - , connected to wordlines and platelines different from one another for storing data, a second reference voltage storage part 8 having a plurality of transistors Q28.about.Q29 and capacitors C9.about.C10 for being in storage of a logic value "1" and a logic value "0" in adjacent bit lines, and a second sense amplifier part 9 having a plurality of transistors Q16.about.Q25 and N-sense amplifiers NSA for sensing a data in the second main cell array part 7.
The operation of the aformementioned background art 1T/1C FRAM will be explained. A writing mode and a reading mode will be explained, separately.
Referring to FIG. 4a, in the writing mode, upon enabling a CSBpad signal, a chip enable signal, from "high" to "low" externally, a writing mode enable signal WEBpad also transits from "high" to "low", to begin the writing mode. And, address decoding is begun, to transit from "low" to "high" on a selected line to select a cell. During the wordline is held at "high", a corresponding plateline P/L is applied of an interval of "high" signal and an interval of "low" signal in a sequence. And, for writing a logic "1" or "0" on the selected cell, "high" or "low" signal is applied to a corresponding bitline synchronous to the writing enable signal. Namely, if "high" signal is applied to the bitline for writing a logic value "1" the logic value "1" is written on the ferroelectric capacitor within an interval of the wordline being "high" at a time when the plateline signal is "low", and for writing logic value "0", if a "low" signal is applied to the bitline, a logic value "0" is written in the ferroelectric capacitor when the plateline signal is "high". Thus, either a logic value "1" or a logic value "0" is written.
The reading operation is carried out as follows.
Referring to FIG. 4b, when CSBpad signal, a chip enable signal, is enabled from "high" to "low" externally, before selection of a corresponding wordline, all bitlines are equalized to "low" by an equalizer signal. That is, in FIG. 3, when "high" signal is applied to the equalizer part 4 and "high" signal is applied to transistors Q19 and Q20, grounding the bitlines through the transistors Q19 and Q20, the bitlines are equalized to "low". Transistors Q5, Q19 and Q20 are turned off, disabling corresponding bitlines, and address is decoded for transiting a corresponding wordline from "low" to "high", to select a corresponding cell. Then, a "high" signal is applied to a plateline of the selected cell, to cancel data corresponding to a logic value "1" stored in an FRAM. If the FRAM is in storage of a logic value "0", a data corresponding to it will not be canceled. A cell with a canceled data and a cell with a data not canceled provide signals different from each other according to the aforementioned hysteresis loop principle. Data provided through bitline is sensed by the sense amplifier of a logic value "1" or "0". That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from "d" to "f", and the case of a data not canceled is a case when a state is changed from "a" to "f", if the sense amplifier is enabled after a certain time, in the case of the canceled data, the data is amplified to provide a logic value "1", and, in the case of the data not canceled, the data is amplified to provide a logic value "0". After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during "high" is applied to a corresponding line, the plateline is disabled from "high" to "low".
However, in the background art 1T/1C FRAM, in which the reference cell is operative more than the main memory cell, the reference cell degrades rapidly, providing an unstable reference voltage. And, regulating of the reference voltage by using a voltage regualting circuit is also not stable as it influced from an external power characteristic and noise. The one that is suggested considering all practically applicable solutions(an extent of development of substitutional electrode materials, a device packing density, a stability of ferroelectric thin film, an operational reliability and etc.,) in place of the background art 1T/1C FRAM having the aforementioned problems, is the 2T/2C FRAM.
FIG. 5 illustrates an array of the background art 2T/2C FRAM cells, FIG. 6a illustrates timings of different signals provided for explaining a writing on the background art 2T/2C FRAM cell, and FIG. 6b illustrates timings of different signals provided for explaining a reading from the background art 2T/2C FRAM cell.
Referring to FIG. 5 the array of the background art 2T/2C FRAM cells is provided with a plurality of wordlines W/L arranged in one direction spaced at fixed intervals, a plurality of platelines P/L arranged parallel to the wordlines between each of the wordlines W/L, and a plurality of bitlines and bitbarlines B1, BB1, B2, BB2 arranged in succession and in a direction vertical to each of the wordlines W/L and the platelines P/L spaced at fixed intervals. And, gate electrodes of the two transistors in a unit memory cell are connected to an adjacent wordline W/L in common, source electrodes of the transitors are connected to an adjacent bitline B and bitbarline BB respectively, and drain electrodes of the transistors are connected to first electrodes on two capacitors respectively, while second electrodes of the capacitors are connected to an adjacent plateline P/L in common.
A driving circuit and operation of the array of the background art 2T/2C FRAM cells will be explained.
Different from the array of the background art 1T/1C FRAM cells, the array of the background art 2T/2C FRAM cells writes and reads a logic value "1" or "0". That is, referring to FIG. 6a, in a writing mode, when a CSBpad signal, a chip enable signal, is transited from "high" to "low" externally, the array is enabled, and, on the same time, a writing mode enable signal WEBpad is also transits from "high" to "low", to provide "high" and "low" or "low" and "high" signals to the bitline and the bitbarline according to a logic value intended to write. Then, an address decoding is begun to transit a wordline of a seclected cell from "low" to "high", to select the cell. Within an interval in which the wordline is held at "high", a corresponding plateline P/L is applied to a fixed interval of "high" signal and a fixed interval of "low" signal in successon. That is, for writing a logic value "1", "high" signal is applied to a bitline B-n and "low" signal is applied to a bitbarline BB-n, and for writing a logic value "0", "low" signal is applied to a bitline B-n and "high" signal is applied to a bitbarline BB-n. Thus, either a logic value "1" or a logic value "0" is written.
The operation for reading a data from the cell will be explained.
Referring to FIG. 6b, when a CSBpad signal, a chip enable signal, is transited from "high" to "low" externally, a read mode is enabled. That is, a write mode enable signal WEBpad is transisted from "low" to "high", finishing the write mode and enabling a read mode. Before selection of a required wordline, all bitlines are equalized to "low" by an equalizer signal identical to the operation of the 1T/1C FRAM shown in FIG. D3. After completion of the equalizing to "low", address is decoded to transit a signal on the required wordline from "low" to "high", selecting a wanted cell. And, "high" signal is applied to a plateline of the selected cell to cancel a data on the bitline or the bitbarline. That is, if a logic value "1" is written, a data in a capacitor connected to the bitline will be canceled, and if a logic value "0" is written, a data in a capcitor connected to the bitbarline will be canceled. Thus, depending on the data canceled of the data on the bitline or on the bitbarline, a value different from each other is provided according to the hysteresis loop principle. When the data provided through either bitline or the bitbarline is sensed by the sense amplifier, the data value will be either logic "1" or logic "0". After the sense amplifier amplifies and provides the data, since the cell should have the data recovered, during the required wordline is applied of "high", the plateline is disabled from "high" to "low".
The background art FRAMs and circuits for driving the same have the following problems.
First, despite of the advantage of data conservation even after power turn off, the cell plate line required separately in the FRAM causes a complicated lay-out as well as a complicated fabrication process, that is a disadvantage in a mass produciton.
Second, the reception of control signals of the wordlines and the plateline different from each other in data reading and writing coming from the use of a separate plateline degrades an efficiency as a memory device due to a difference of signal paths.
Third, the use of one reference cell in reading a few hundreds of main memory under a state properties of the ferroelectric film is not perfectly secured, resulting in much more operation of the reference cell, causes a rapid degradation of the reference cell, that leads to have an unstable reference voltage.
Fourth, the generation of a reference voltage by means of a voltage regulating circuit is not stable because the reference voltage is influenced from external power source characteristic and may be deteriorated by external noises.
Fifth, with the use of CSBpad(chip selection signal) only in enabling a ferroelectric memory, a fast access can not be achieved.